1. Field Of The Invention
The present invention relates to a technique for automatically aligning a semiconductor wafer prior to step-and-repeat microphotolithographic exposure, and for automatic die-by-die alignment during the exposure processing.
2. Description Of The Prior Art
In conventional integrated circuit fabrication, a semiconductor wafer typically undergoes from four to ten major process steps, at each of which steps part of a circuit pattern is exposed from a mask or reticle onto the wafer. In "step-and-repeat" processing, an enlarged mask, typically ten times actual size, contains the circuit pattern for one or a very few individual die sites. The wafer is positioned at one of these die sites, and a reduced image of the mask pattern is exposed onto photoresist covering the wafer through a size reducing lens system. The wafer is then stepped to the next die site and the mask exposure is repeated. This step-and-repeat operation continues until all die sites have been exposed.
For optimum yield, the pattern images of each subsequent mask must be formed in perfect registration with the circuit elements formed during prior steps. As a minimum, this requires that prior to exposure by each subsequent mask, the wafer must be perfectly located and aligned in the step-and-repeat apparatus, and must be accurately stepped from one die site to the next. Optimally, an individual alignment should be performed at each die site. Die-by-die alignment is preferred, since distortion of the wafer may occur during individual process steps. As a result, although exact uniform spacing existed between the circuits at individual die sites during earlier process steps, the spacing may differ slightly during successive steps. If the wafer is then merely moved a fixed distance from site to site, without individual site alignment, misregistration may occur at some or all of the die sites during exposure to the masks used for these later processing steps.
The speed at which both initial wafer alignment and die-by-die alignment is achieved must be minimized. Step and repeat exposure systems are very expensive, typically costing hundreds of thousands of dollars. For cost effective use of such equipment, the time for processing each wafer must be minimized. Optimally, all alignment operations shold be automated so that no operator intervention is required throughout the entire wafer alignment and step-and-repeat exposure operation. Such cost effectiveness is not achieved if, for example, it is necessary for an operator to use a joy stick to position and align the wafer while watching an alignment target on a video display. An object of the present invention is to provide a technique for automatic alignment of each wafer in the step-and-repeat apparatus without any operator intervention.
Techniques for die-by-die alignment have been suggested in the past. These are taught e.g., in the U.S. Pat. No. 4,052,603 to Karlson, U.S. Pat. No. 4,153,371 to Koizumi. Die-by-die alignment also is shown in the copending U.S. patent application Ser. No. 330,498, a continuation of Ser. No. 238,148 entitled SINGLE LENS REPEATER assigned to TRE Corporation, the assignee of the present application.
Advantageously, the initial or "A-level" mask contains both the circuit pattern for the intial processing step, and a wafer target pattern which is exposed onto the wafer along with the circuit pattern itself. Typically this wafer alignment target is exposed in the alley along which the wafer ultimately will be scribed to separate the individual circuit chips.
During the initial processing step the exposed wafer alignment target is subjected the same processing as the circuit itself. For example, this may comprise the diffusion of an N- or P- type dopant into the semiconductor wafer. In this manner, a die alignment target is formed in the wafer at each die site. It is this alignment target which is used during subsequent mask exposure steps to accomplish die-by-die alignment. Two or more of the same or different wafer alignment targets also may be used for accurate prealignment of the wafer at the beginning of each successive mask exposure operation.
Beginning with the second or "B-level" mask, each mask is provided both with the requisite circuit pattern and with a reticle alignment window or target. For die-by-die alignment, when the wafer is stepped to each die site, appropriate viewing optics are used simultaneously to view the alignment target on the wafer and the complementary alignment target or window on the reticle. The wafer is then moved relative to the mask until perfect alignment is achieved. An object of the present invention is to accomplish such die-by-die alignment automatically.
To best facilitate such step-and-repeat exposure operation, it is advantageous to prealign the wafer with the X- and Y- axes of the exposure system. In this way, the circuit patterns at each die site can be aligned in an orthogonal matrix, with a substantially fixed distance between each die site. In a typical apparatus, each wafer is roughly aligned prior to transport onto the exposure table by detection of a flat sector on the wafer. The roughly aligned wafer is transported onto a table that is accurately positionable beneath the system exposure lens. Advantageously, this table not only can be moved accurately along the X- and Y- axes of the system, but also can be rotated sufficiently to eliminate any rotational error that may exist when the wafer is first mechanically transported onto the table.
Another object of the present invention is to achieve automatic, precise and accurate prealignment of the wafer after it is placed onto the wafer table, but prior to circuit exposure. Another objective is to achieve such prealignment by reference to an arbitrary two or more of the die site alignment targets. These are referred to herein as "global" targets, and a further object of the present invention is to provide an automatic system for locating, identifying and verifying such global targets as part of the prealignment process. A further objective is to provide a search scheme for locating the global targets in the event that the mechanical prealignment of the wafer was not error free.
To accomplish such automatic alignment, the wafer target and the reticle window or target are viewed simultaneously using a video camera. The video scan image is converted to a digital format for appropritate data processing. A further object of the present invention is to provide appropriate methods for handling this digitized data to accomplish wafer alignment.
A problem encountered by such a system is that of distinguishing the actual wafer target from other indicia or circuit elements on the wafer. In a manual, joy stick-controlled system, an operator observing the video display generally can visually distinguish a true target from other indicia on the wafer. Such human pattern recognition capability cannot readily be machine synthesized. However, a further object of the present invention is to provide an automated technique that is capable of distinguishing between an actual wafer alignment target and other indicia on the wafer.
A further problem which complicates wafer alignment concerns the ability to distinguish the wafer target from the surrounding area on the wafer. Recall that the target itself is formed on or within the wafer by certain process steps such as diffusion. Thus the target must be recognized by distinguishing between the amplitude or phase of light reflected from the target itself and light reflected from areas on the wafer immediately adjacent to the target. For most process steps, the difference in reflected light intensity is sufficiently great so as to enable the target readily to be seen. But this may not be the case at other process steps. As a typical example, prior to the process step in which electrical (ohmic) connections are made between circuit elements, a metalized layer is deposited onto the wafer. This layer is highly light reflective. Consequently, the difference in intensity between light reflected from the wafer target and light reflected from the surrounding region on the wafer is very slight.
Distinguishing such target may be aided by detecting differences in phase of the light reflected from the target and that reflected from the surrounding region. This approach is disclosed in the co-pending U.S. patent application Ser. No. 248,605 now U.S Pat. No. 4,419,013 entitled ALIGNMENT SYSTEM FOR SEMICONDUCTOR MANUFACTURING APPARATUS also assigned to TRE Corporation, the assignee of the present application. A further object of the present invention is to provide an automated technique for recognizing a wafer alignment pattern even with minimal difference in intensity from the background.